Re: [myhdl-list] reusable blocks with different interfaces

[Josy B. <jos...@gm...>]

Keerthan JC <jckeerthan <at> gmail.com> writes:

> 
> 
> Interfaces signals are converted with dots replaced to underscores. If 
you follow the qsys naming conversions(aso,asi,avm,avs), qsys will 
automatically detect the interfaces.
> 
> 

That's not what I meant: I'm currently working on a Python/MyHDL 
extension to generate the xx_hw.tcl files from within MyHDL (this would 
not have to use that ugly, perfectly useful for automated recognition 
but still ugly, naming convention). The xx_hw.tcl will not only guide 
the elaboartion, but also call back on the MyHDL module to generate the 
bespoke VHDL code.

My 'wish' is the following:
Henry is talking about extending the interfaces concept of MyHDL. When 
converted to VHDL this would result in having structured types (e.g. a 
record) as ports. My 'sigh' is that Qsys only handles std_logic_vector 
as the data type. So it would be great if we could automate the 
conversion between the required std_logic_vector port in VHDL (or even 
Verilog) and the inherently more useful interface object in MyHDL. See 
it as an interface within an interface (or in VHDL: a record in a 
record)

Regards,

Josy