Re: [myhdl-list] reusable blocks with different interfaces

[Keerthan JC <jck...@gm...>]

Interfaces signals are converted with dots replaced to underscores. If you
follow the qsys naming conversions(aso,asi,avm,avs), qsys will
automatically detect the interfaces.

On Fri, Jan 16, 2015 at 2:23 PM, Josy Boelen <jos...@gm...> wrote:

> Henry Gomersall <heng <at> cantab.net> writes:
>
> ><snip>
> > def interface_processor(input_interface, output_interface, clock,
> reset):
> >
> >      process_blocks = []
> >      for attr_name in input_interface.__dict__:
> >          locals()['input_' + attr_name] = getattr(input_interface,
> > attr_name)
> >          locals()['output_' + attr_name] = getattr(output_interface,
> > attr_name)
> >
> >          if isinstance(locals()['input_' + attr_name],
> > myhdl._Signal._Signal):
> >
> >              process_blocks.append(
> >                  single_signal_processor(
> >                      locals()['input_' + attr_name],
> >                      locals()['output_' + attr_name], clock, reset))
> >
> >      return process_blocks
> ><snip>
>
> It would be nice if we also had a 'magic' way to export / import the
> interfaces as a std_logic_vector. As this is what Altera's Qsys
> understand. I doubt that Xilinx' IP Integrator will be any smarter.
>
> Regards,
>
> Josy
>
>
>
>
>
>
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-- 
have a nice day
-jck