Re: [myhdl-list] reusable blocks with different interfaces

[Christopher F. <chr...@gm...>]

<resending ???>
On 1/15/2015 1:17 PM, Henry Gomersall wrote:
> On 15/01/15 19:15, Henry Gomersall wrote:
>>        @always_seq(clock.posedge, reset)
>>        def block():
>>            output_interface.next = input_interface
>
> To be clear the important line is above. I want to assign a whole
> interface at once, without reference to its attributes.
>

But there are other ways to achieve this, the elaboration
phase (outside the generator).  The following is an example.
*NOTE*, I did this extremely quick as an example what could
be done.  May or may not be desirable or fit your actual use.
Also note, this will work fine inside a design but not so
good for top-level ports.

Regards,
Chris

##############################
Example
##############################

from myhdl import *

class Interface(object):
     def __init__(self):
         self.a = Signal(intbv(0)[5:])
         self.b = Signal(intbv(0)[7:])

def m_copy(clock, reset, x,y):
     @always_seq(clock.posedge, reset=reset)
     def rtl():
         y.next = x
     return rtl

def m_interface_copy(input_interface, output_interface, clock, reset):

     gc = []
     for k,v in input_interface.__dict__.iteritems():
         if isinstance(v, SignalType):
             print(k,v)
             gc.append(m_copy(clock, reset, input_interface.__dict__[k], 
output_interface.__dict__[k]))

     return gc

foo = Interface()
bar = Interface()
clock = Signal(bool(1))
reset = ResetSignal(bool(0), active=1, async=False)
toVerilog(m_interface_copy, foo, bar, clock, reset)

('a', Signal(intbv(0L)))
('b', Signal(intbv(0L)))
Out[14]:
[<myhdl._always_seq._AlwaysSeq at 0x9ecaac8>,
  <myhdl._always_seq._AlwaysSeq at 0x9a026d8>]

%less m_interface_copy.v
// File: m_interface_copy.v
// Generated by MyHDL 0.9dev
// Date: Thu Jan 15 13:39:12 2015


`timescale 1ns/10ps

module m_interface_copy (
     clock,
     reset,
     gc_0_x,
     v,
     gc_0_y,
     gc_1_y
);


input clock;
input reset;
input [4:0] gc_0_x;
input [6:0] v;
output [4:0] gc_0_y;
reg [4:0] gc_0_y;
output [6:0] gc_1_y;
reg [6:0] gc_1_y;






always @(posedge clock) begin: M_INTERFACE_COPY_GC_0_RTL
     if (reset == 1) begin
         gc_0_y <= 0;
     end
     else begin
         gc_0_y <= gc_0_x;
     end
end


always @(posedge clock) begin: M_INTERFACE_COPY_GC_1_RTL
     if (reset == 1) begin
         gc_1_y <= 0;
     end
     else begin
         gc_1_y <= v;
     end
end

endmodule