[myhdl-list] reusable blocks with different interfaces

[Henry G. <he...@ca...>]

At risk of asking an XY problem (in which I describe a different problem 
to the more fundamental one), I would like to know if it is possible 
with MyHDL 0.9 to define a reusable convertible block that does 
something like the following:

from myhdl import *

class Interface(object):
     def __init__(self):
         self.a = Signal(intbv(0)[5:])
         self.b = Signal(intbv(0)[7:])

def block_factory(input_interface, output_interface, clock, reset):

     @always_seq(clock.posedge, reset)
     def block():
         output_interface.next = input_interface

     return block

foo = Interface()
bar = Interface()
clock = Signal(bool(1))
reset = ResetSignal(bool(0), active=1, async=False)

toVerilog(block_factory, foo, bar, clock, reset)

Running this yields "Object type is not supported in this context: 
output_interface".

Now, my use case for this is to create a block that takes an interface 
as its argument, and from which I can create a buffer (or a small FIFO) 
of the attributes defined by the interface. The point is to match the 
propagation of state information alongside data processing inside a 
pipeline.

The problem is that although the interface for every instantiation is 
known at conversion time, it is not necessarily known when I create the 
factory. Short of creating an uber-interface with every possible state 
signal in there, I can't see how to do this.

Obviously, I could create a different block for every interface, but I 
was wondering if I could avoid that.

I've considered other options like creating a single bit vector 
containing all the same info as the Interface, but this seems rather 
backwards.

I feel there must be a solution here!

Cheers,

Henry