Re: [myhdl-list] calls with mismatched arguments being passed quietly
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From: Josy B. <jos...@gm...> - 2015-01-12 08:34:34
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Henry Gomersall <heng <at> cantab.net> writes: > The warning you highlight is a red herring as it's referring to the > outer-most closure. > > Consider the following change: > > def Test(an_arg, clock, reset): > > <at> always_seq(clock.posedge, reset=reset) > def test_case(): > if an_arg: > bleh() > > return test_case > > This converts with no warnings but the same symptoms. > > You're quite right this should be picked up by testing, but I don't > think it should pass quite so quietly as it does. > > Cheers, > > Henry > > ------------------------------------------------------------------------- Henry, I posted two follow-up messages detailing my further investigations, but Gmane seems to have eaten them ... I don't have access to my 'home' machine, so I try to recall what I did yesterday evening. It doesn't pass quietly though: MyHDL gives a warning that the argument is not used. Another Red Herring. I have a rule that my code must be warning free. 'A Warning is an Error Waiting to Happen' is a quote a picked up in the eighties. I ran it through Quartus II 14.1's Synthesis and this complains about a 'assignment error' as MyHDL generated in the procedure code (not a function as it doesn't return a value) a '<=' for what apparently is a 'variable'. So this seems to be another bug in MyHDL. I then further modified the Python code and 'corrected' the missing argument. It will then convert again, but with another warning: that the top level port test_arg is an 'inout'. Again 'inout' ports are a Red Red Herring. Running it through the Synthesis yields another error as now the conversion is missing the 'signal' argument. If we correct that in the VHDL code it will synthesize but the RTL schematic doesn't look pretty, which it can't be as we now have TriState signals. All in all, this now contrived example has taken us from Scylla to Charybdis :) Regards, Josy |