Re: [myhdl-list] calls with mismatched arguments being passed quietly

[Josy B. <jos...@gm...>]

Henry Gomersall <heng <at> cantab.net> writes:

> 
> Should a call to a function with mismatched arguments be passed 
quietly 
> as it sometimes is currently?
> 
> consider:
> 
> from myhdl import *
> 
> def bleh(test_arg):
>      test_arg.next = not test_arg
> 
> def Test(an_arg, clock, reset):
> 
>       <at> always_seq(clock.posedge, reset=reset)
>      def test_case():
>          bleh()
> 
>      return test_case
> 
> test_arg = Signal(bool(0))
> clock  = Signal(bool(0))
> reset = ResetSignal(0, active=0, async=True)
> 
> inc_inst = toVHDL(Test, test_arg, clock, reset)
> 
> The python parser has no problem with this because test_arg is in the 
> global namespace. However, the converted code just completely ignores 
> the function call (putting only ';' ) :
> 
> TEST_TEST_CASE: process (clock, reset) is
> begin
>      if (reset = '0') then
>      elsif rising_edge(clock) then
>          ;
>      end if;
> end process TEST_TEST_CASE;
> 
> toVerilog similarly misses out the argument list (though it has the 
> function name).
> 
> I would suggest this can be picked up at the end of the FunctionType 
> case in visit_Call with a test of equality between len(node.args) and 
> len(tree.argnames) here:
> 
https://bitbucket.org/jandecaluwe/myhdl/src/f7a6b2ef05bbf418349d8b0021d8
1b4fc83b8ce0/myhdl/conversion/_analyze.py?at=0.9-dev#cl-657
> 
> I can do this and raise a pull request, but am I missing something 
about 
> the handling of function calls?
> 
> Cheers,
> 
> Henry
> 
> ----------------------------------------------------------------------
When I copy/paste the code in PyDev/Eclispe I get a warning of unused 
argument ...

MyHDL will convert the code as is, beit with a warning: '** 
ToVHDLWarning: Port is not used: an_arg'
---
TEST_TEST_CASE: process (clock, reset) is
begin
    if (reset = '0') then
    elsif rising_edge(clock) then
        MYHDL2_bleh;
    end if;
end process TEST_TEST_CASE;

end architecture MyHDL;
----
Notice that in MyHDL 0.9 the procedure (as there is nothing to be 
returned) all is also in the converted VHDL (as you say there is in the 
Verilog code)

If we are careful and use different declaration and instantiating names 
to avoid the global namespace pitfalss e.g.:
from myhdl import *
 
def bleh(test_arg):
    test_arg.next = not test_arg

def Test(an_arg, clock, reset):

    @always_seq(clock.posedge, reset=reset)
    def test_case():
        bleh()

    return test_case

arg = Signal(bool(0))
clock  = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)

inc_inst = toVHDL(Test, arg, clock, reset)

MyHDL will come up with an exception: 'myhdl.ConversionError: in file 
C:\qdesigns\MyHDL\Source\thg.py, line 4:
    Local variable may be referenced before assignment: test_arg
' 
If we write a self-checking test-bench the 'error' will be flagged too 
as the simulation will fail.(I'm not going to do this exercise as I 
would solve the problem early on by correcting the warning given by 
Pydev in Eclipse)

Regards,

Josy