Re: [myhdl-list] Some name mangling on the constants needed for VHDL

[Henry G. <he...@ca...>]

On 09/01/15 17:10, Christopher Felton wrote:
> <snip>
>> >
>> >It's interesting that it shows up as a "constant" though. I don't see
>> >how that fits with interfaces.
>> >
> You might be correct, I probably jump to the
> conclusion that the Interface code that walks
> objects and their attributes might of caused
> the problem.  Looks like I have some homework.

The relevant magic seems to be
for VHDL: 
https://bitbucket.org/jandecaluwe/myhdl/src/f7a6b2ef05bbf418349d8b0021d81b4fc83b8ce0/myhdl/conversion/_toVHDL.py?at=0.9-dev#cl-1273
(interestingly it's a line number offset from my local code)

for Verilog: 
https://bitbucket.org/jandecaluwe/myhdl/src/f7a6b2ef05bbf418349d8b0021d81b4fc83b8ce0/myhdl/conversion/_toVerilog.py?at=0.9-dev#cl-991

which are just walked to during the ast traversal at write out. It seems 
objects which are recognized as integers are simply assumed to be 
constant, which seems sensible.

The issue only then is the name is not necessarily valid, so some 
mangling is necessary.

The signal name mangling is done here:
https://bitbucket.org/jandecaluwe/myhdl/src/f7a6b2ef05bbf418349d8b0021d81b4fc83b8ce0/myhdl/conversion/_analyze.py?at=0.9-dev#cl-118

which calls a function defined in that file. It would be simple to call 
that function in the toVHDL getNames function to perform necessary name 
mangling.

Cheers,

Henry

Is the

Cheers,

Henry