Re: [myhdl-list] Some name mangling on the constants needed for VHDL

[Henry G. <he...@ca...>]

On 09/01/15 16:43, Christopher Felton wrote:
> On 1/9/2015 10:27 AM, Henry Gomersall wrote:
>> >I was pleased to find that now constants are allowed in 0.9.
>> >
>> >The problem is if the constant name is simply dumped passed in as the
>> >constant name in VHDL. So the following happens:
>> >
>> >class Bleh(object):
>> >       meh = 12
>> >
>> >eep = Bleh()
>> >
> <snip>
>> >
>> >constant eep.meh: integer := 12;
>> >
>> >I understand some name mangling is probably required here to make the
>> >name acceptable to the standard.
>> >
> This isn't officially supported and the above
> is a manifestation of the "Interface" support.
>
> Note, this doesn't mean it is not a good idea
> to support this but for now it is not.  A work
> around is to dereference constants and variables
> (i.e. non Signals) locally.
>
>       meh = eep.meh
>       @always_seq(clock.posedge ...)
>       def inclogic():
>       # ...
>               foo.next = meh

Yeah, I thought of that solution. The problem is that I actually want to 
use an IntEnum class in place of loads of constants being defined.

It's not a major issue, but something that it would be nice if it worked.

> I posted another example that had a similar
> side effect.
> http://article.gmane.org/gmane.comp.python.myhdl/3716/match=interesting
I saw your post, but wasn't at the time able to grasp the significance. 
Now I am :)

It's interesting that it shows up as a "constant" though. I don't see 
how that fits with interfaces.

Cheers,

Henry