[myhdl-list] Initial values of signals

[Edward V. <dev...@sb...>]

Hello all,

How do you set signals values to the initial value in myhdl?

After adding the last 3 values to the package pck_xess_jpeg_top  that is generated
with the a python file.
I started getting the following 2 errors (see below)
Line 85: Formal <y_u> has no actual or default value.
Line 86: Formal <eog> has no actual or default value.
This can be corrected by changing the lines 91 and 92 as shown below
        y_u: in unsigned(15 downto 0);
        eog: in std_logic:= '0'
to
        y_u: in unsigned(15 downto 0):= (others => '0');
        eog: in std_logic
I was already needing to change signal instance_1_reset_ctn: unsigned(3 downto 0);
signal instance_1_reset_ctn: unsigned(3 downto 0):= "0000"; to get my simulation to work
correctly.
All help is welcomed.
Thanks
entity xess_jpeg_top is
    port (
        clk_fast: in std_logic;
        addr_r: out unsigned(22 downto 0);
        addr_x: inout unsigned(22 downto 0);
        state_r: inout t_enum_t_State_1;
        state_x: inout t_enum_t_State_1;
        dataToRam_r: inout unsigned(15 downto 0);
        dataToRam_x: inout unsigned(15 downto 0);
        dataFromRam_r: out unsigned(15 downto 0);
        dataFromRam_x: inout unsigned(15 downto 0);
        sig_in: inout unsigned(51 downto 0);
        noupdate_s: out std_logic;
        res_s: inout signed (15 downto 0);
        res_u: out unsigned(15 downto 0);
        jp_lf: in unsigned(15 downto 0);
        jp_sa: inout unsigned(15 downto 0);
        jp_rh: in unsigned(15 downto 0);
        jp_flgs: inout unsigned(3 downto 0);
        reset_col: out std_logic;
        rdy: in std_logic;
        addr_not_reached: in std_logic;
        offset_r: inout unsigned(22 downto 0);
        offset_x: inout unsigned(22 downto 0);
        dataFromRam_s: in unsigned(15 downto 0);
        done_s: in std_logic;
        wr_s: out std_logic;
        rd_s: out std_logic;
        sum_r: inout unsigned(15 downto 0);
        sum_x: inout unsigned(15 downto 0);
        empty_r: out std_logic;
        full_r: out std_logic;
        enr_r: inout std_logic;
        enw_r: inout std_logic;
        dataout_r: inout unsigned(15 downto 0);
        datain_r: inout unsigned(15 downto 0);
        empty_x: inout std_logic;
        full_x: inout std_logic;
        enr_x: inout std_logic;
        enw_x: inout std_logic;
        dataout_x: inout unsigned(15 downto 0);
        datain_x: inout unsigned(15 downto 0);
        col_r: inout unsigned(7 downto 0);
        col_x: inout unsigned(7 downto 0);
        row_r: inout unsigned(7 downto 0);
        row_x: inout unsigned(7 downto 0);
        rst: out std_logic;
        y_u: in unsigned(15 downto 0);
        eog: in std_logic
    );

 





 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613