Re: [myhdl-list] std_logic_vector

[Josy B. <jos...@gm...>]

Edward Vidal <develone <at> sbcglobal.net> writes:
> Is there a way to have mix of unsigned and std_logic_vector?I have a 
top_level that has only 1 toVHDL statement. 

No, all ports of the module will be std_logic_vector in stead of unsigned.

> For now only 1 signal needs to be std_logic_vector to match someone else 
code.  When I break it up to 7 toVHDL 1 statement fails since a
>  variable is _enumPortTypeSet AssertionError.I am correct in thinking 
that toVHDL.numeric_ports = False is only for the next toVHDL statement.

I don't think you can break up the toVHDL() call. I guess the best idea is 
to accept either the all-unsigned (or all-std_logic_vector) ports and 
write a small VHDL wrapper around either the MyHDL module or around the 
'someone else's' module.

>Also did not understand the Qsys comment I am using a Xilinx product 
spartan 6.  Web search appears to be for Altera product.

Indeed Qsys is for Altera products. It is GUI to connect Building Blocks. 
Saving a lot of typing.

Regards,

Josy