[myhdl-list] std_logic_vector

[Edward V. <dev...@sb...>]

 Hello
Josy thanks for the reply. 
Is there a way to have mix of unsigned and std_logic_vector?
I have a top_level that has only 1 toVHDL statement.  For now only 1 signal needs to be std_logic_vector to match someone else code.  
When I break it up to 7 toVHDL 1 statement fails since a variable is _enumPortTypeSet AssertionError.
I am correct in thinking that toVHDL.numeric_ports = False is only for the next toVHDL statement.
Also did not understand the Qsys comment I am using a Xilinx product spartan 6.  Web search appears to be for Altera product.
Thanks
I am starting to think that I might be making progress.  

Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613