Re: [myhdl-list] FW: Std_logoc_vector

[Josy B. <jos...@gm...>]

Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> ----Forwarded Message----
> From: develone <at> sbcglobal.net
> To: myhdl-list-request <at> lists.sourceforge.net
> Sent: Tue, Jan 6, 2015 4:03 PM CST
> Subject: Std_logoc_vector
> 
> Hello.
> How do you get a signal to be std_locic_vector instead of unsigned or 
signed to match others code that is
> defined as std_logic_vector. Thanks
> 
> 
Use this:
-------
        # force std_logic_vectors instead of unsigned in Interface as 
Qsys wants this
        toVHDL.numeric_ports = False
        toVHDL( ... )

------
I'm not sure whether it is documented, but it works (at least in MyHDL 
0.9)

Regards,

Josy