Re: [myhdl-list] Lost in conversion ... _error.SignalInMultipleLists

[Christopher F. <chr...@gm...>]

On 1/5/2015 2:56 AM, Josy Boelen wrote:
<snip>
> ---
> Can somebody shed some light?
>

I didn't work through your print trace or what
the conversion code is trying to do.  But here
is an example that generates the same error.

     from myhdl import *

     def m_multi_list(clock, reset, x, y):
         los1 = [Signal(bool(0)) for _ in range(4)]
         sig_in_two = los1[0]
         los2 = [sig_in_two] + [Signal(bool(0)) for _ in range(3)]

         @always_seq(clock.posedge, reset=reset)
         def rtl():
             y.next = los1[x] and los2[x]

         return rtl

     clock = Signal(bool(0))
     reset = ResetSignal(0, active=0, async=True)
     x = Signal(intbv(0, min=0, max=4))
     y = Signal(bool(0))
     toVHDL(m_multi_list, clock, reset, x, y)


Do you have an example of the failing code?
This is probably one of those cases where it
will simulate ok (no restriction for a signal
in a single list) but will not convert.


Regards,
Chris