Re: [myhdl-list] ISE 14.7 and FSM

[Edward V. <dev...@sb...>]

The python file is in the same folder as the https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/XESS_SdramSPInst/xess_jpeg_top.vhd

https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/XESS_SdramSPInst/xess_jpeg_top.py  

The FSM that works okay in a simulation is https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/jpeg_top.py with the test bed https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/simulation/jpegprocess_tb.vhd.  
This one is not using sdram.  

 I did notice that the one that is  not working has several lines without a ";" is this normal.  The steps to change the https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/jpeg_top.py to 
generate the one with the non working FSM are in the previous e-mail or at the https://github.com/develone/jpeg-2000-test/commits/master/jpeg2k/XESS_SdramSPInst/xess_jpeg_top.py history tab.
Thanks,

Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613


On Saturday, December 6, 2014 11:51 AM, Christopher Felton <chr...@gm...> wrote:
 


On 12/6/14, 10:16 AM, Edward Vidal wrote:
> Hello All,
> Fairly new to both VHDL and myhdl.
> I would appreciate any and all help. Thanks in advance.
> I have created other FSM that I used in simulation and it worked okay.
> I am using ISE 14.7 for a Spartan6 XC6SLX9.

Simulation works ok but when you try and synthesize
the design you get errors (assumes conversion works
ok?).

> If I can provide any additional information just let me know.
> Creating a project with xess_jpeg_top.vhd & pck_myhdl_09.vhd will
> synthesize okay.
> The file xess_jpeg_top.vhd is not a package and has the following RTL
> modules.

Is the original source MyHDL source?  Do you have
a link to the original MyHDL?

p.s. the IRC channel #myhdl on freenode can also
be used for real-time discussions.

Regards,
Chris





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