Re: [myhdl-list] ISE 14.7 and FSM

[Christopher F. <chr...@gm...>]

On 12/6/14, 10:16 AM, Edward Vidal wrote:
> Hello All,
> Fairly new to both VHDL and myhdl.
> I would appreciate any and all help. Thanks in advance.
> I have created other FSM that I used in simulation and it worked okay.
> I am using ISE 14.7 for a Spartan6 XC6SLX9.

Simulation works ok but when you try and synthesize
the design you get errors (assumes conversion works
ok?).

> If I can provide any additional information just let me know.
> Creating a project with xess_jpeg_top.vhd & pck_myhdl_09.vhd will
> synthesize okay.
> The file xess_jpeg_top.vhd is not a package and has the following RTL
> modules.

Is the original source MyHDL source?  Do you have
a link to the original MyHDL?

p.s. the IRC channel #myhdl on freenode can also
be used for real-time discussions.

Regards,
Chris