[myhdl-list] Interesting ...

[Christopher F. <chr...@gm...>]

Hmmm, I didn't know what to expect but I wasn't
expecting this:

In [22]: def m_nonlocal(clock, reset, x, y, z):
     ...:     class nonlocal:
     ...:         cnt = 0
     ...:
     ...:     @always_seq(clock.posedge, reset=reset)
     ...:     def rtl():
     ...:         nonlocal.cnt += 1
     ...:         if nonlocal.cnt > 10:
     ...:             z.next = x + y
     ...:             nonlocal.cnt = 0
     ...:     return rtl
     ...:

In [23]: from myhdl import *

In [24]: clock = Signal(bool(0))
     ...: reset = ResetSignal(0, 0, True)
     ...: x,y,z = [Signal(intbv(0, min=-80, max=80)) for _ in range(3)]
     ...: toVerilog(m_nonlocal, clock, reset, x, y, z)
     ...:
Out[24]: <myhdl._always_seq._AlwaysSeq at 0xa2e10b8>

In [25]: %less m_nonlocal.v
// File: m_nonlocal.v
// Generated by MyHDL 0.9dev
// Date: Fri Nov 21 16:32:28 2014
// <snip a bunch of stuff ... >

always @(posedge clock, negedge reset) begin: M_NONLOCAL_RTL
     reg nonlocal.cnt;
     if (reset == 0) begin
         z <= 0;
     end
     else begin
         nonlocal.cnt = nonlocal.cnt + 1;
         if ((nonlocal.cnt > 10)) begin
             z <= (x + y);
             nonlocal.cnt = 0;
         end
     end
end

endmodule