[myhdl-list] Signal has multiple drivers

[Edward V. <dev...@sb...>]

Hello all,
Fairly new to vhdl.  Using a structural model with 8 instances.  Everything was working okay.
Started getting a message the Signal has multiple drivers.
Found a posting http://comments.gmane.org/gmane.comp.python.myhdl/1999
from Chris Felton to use a mux.

I see in the package generated with toVHDL
signal instance_7_addr_r: unsigned(5 downto 0); which is used by JPEG_TOP_INSTANCE_1_SDRAM_RD and
JPEG_TOP_INSTANCE_7_FILE_RD.

What I do not see in the package is the code for the muxLogic.

    @always_comb
    def muxLogic():
        addr_r.next = addr_r1
        if sel == 1:
            addr_r.next = addr_r2
    return muxLogic    
which was part of JPEG_TOP_INSTANCE_7_FILE_RD.

def read_file_sdram(clk_fast, rst, eog, we_sdram, rst_file_in, addr_r1, addr_r2, sel ):
    addr_r = Signal(intbv(0)[6:])
    @always(clk_fast.negedge)
    def file_rd():
        if (rst_file_in == 0):
            rst.next = 1
            addr_r.next = 0
            we_sdram.next = 1
        else:
            if (rst == 1):
                rst.next = 0
            elif (eog == 0):
                if (addr_r <= 48):
                    
                    addr_r.next = addr_r + 1
            else:
                we_sdram.next = 0
    return file_rd
    @always_comb
    def muxLogic():
        addr_r.next = addr_r1
        if sel == 1:
            addr_r.next = addr_r2
    return muxLogic

I am trying to run a simulation using ISE 14.7 at the moment.
I know I need to use addr_r1, addr_r2, and sel for JPEG_TOP_INSTANCE_7_FILE_RD. Which is where is where
I defined the muxLogic.  JPEG_TOP_INSTANCE_7_FILE_RD and JPEG_TOP_INSTANCE_1_SDRAM_RD
both will be used in simulation.  Only JPEG_TOP_INSTANCE_1_SDRAM_RD & JPEG_TOP_INSTANCE_4_FSM will be used
in the bit file.  This uses addr_r which is not part of entity jpeg_top.
Did I put the muxLogic code in the wrong place?
Thanks in advance for any and all help.


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613