Re: [myhdl-list] Using existing HDL modules - part 2

[Christopher F. <chr...@gm...>]

On 11/5/2014 5:57 AM, Mike Gill wrote:
> Thanks to all for the responses to my post of 3rd Nov. I feel a fraud
> because shortly after posting I was able to instantiate an external
> primitive with user defined code by actually reading the manual.
>
> Thanks to Guy for the presentation. I replicated the example in slide 43.
>
> It looks like this example is intended to be simulated but I don't think the
> defined logic function is recognized in MyHDL. The same VHDL file and the
> same "ToVHDLWarning: Port is not used: O" is generated if the logic function
> is replaced with "pass". In
> http://docs.myhdl.org/en/latest/manual/conversion_examples.html#user-defined-code
> it says "...conversion of the ..... function is bypassed..."

Correct, the user-defined code will not be
interpreted, analyzed, etc. by MyHDL.  If you
want to simulate, in MyHDL, you need to define
logic that represents the behavior (no small task
for large IP) or do co-simulation.

>
> I think this topic is important. MyHDL is attractive for algorithm
> development (my personal interest) but I don't see how it could possibly be
> considered for development of a whole fpga project where it controls the top
> level module. It is vital to be able to readily use not only chip primitives
> but also soft IP cores generated by the chip vendor's tool suite, and it
> can't be relied on that everyone involved will know Python.
>

As mentioned the difficulty will be simulation, it
would be a large task (project) to build a fully
compliant Verilog or VHDL simulator in Python that
could read, parse, compile, and simulate the IP.

> Is it possible to have a wrapper function for the user-defined code feature
> along the lines of:
>
> module_inst = include('module_file.v/.vhd', signal_list,  property_list=None)

There is a beta feature where you define the module
to be a Verilog of VHDL instance:

     def VHDL_ENTITY(clock, reset, x, y, z):
         z.driven = True
         @always(clock, reset, x, y)
         def logic():
             pass
         return logic
     VHDL_ENTITY.vhdl_instance = "VHDL_INSTANCE_NAME"

     def m_top(clock, reset, x, y, z):
         g = VHDL_ENTITY(clock, reset, x, y, z)
         return g

     clock = Signal(bool(0))
     reset = ResetSignal(0, 0, True)
     x,y,z = [Signal(intbv(0)[8:]) for _ in range(3)]
     toVHDL(m_top, clock, reset, x, y, z)


https://gist.github.com/cfelton/0792c5823d418afee604

Verilog is the same.  Your MyHDL module will need to have
the same port list but it simplifies, some.  It would
be an unreasonable task to parse the VHDL or Verilog and
determine the ports automatically.

Note, I agree tools to help realize the current state of FPGA
development aren't bad but I don't know if this falls under
the current MyHDL goals (might be an external tool) or if there
are enough developers to generate such tools.

In summary, I don't believe there are any show stoppers but
integration with FPGA IP and 3rd party IP is interesting
when it comes to simulation / verification.


Regards,
Chris