Re: [myhdl-list] VHDL Records

[Christopher F. <chr...@gm...>]

On 11/5/2014 5:27 AM, Wesley New wrote:
> Hi All,
>
> We are sitting with a problem where we wish to use existing VHDL code that
> uses records and wish to pull it into our MyHDL designs with using user
> defined code. Unfortunately it would seem that MyHDL does not support this.
> Is this correct or is there some way to create records out of signals?
>
> Thanks
>

In the user-defined code, any valid HDL can exist.
But the MyHDL converter will not convert anything
to VHDL records.  The converter, for the most part,
attempts to use basic common constructs between Verilog
and VHDL.

The best option is to write a wrapper in  VHDL that
breaks out the signals.


Regards,
Chris