[myhdl-list] Using existing HDL modules - part 2

[Mike G. <mj...@gi...>]

Thanks to all for the responses to my post of 3rd Nov. I feel a fraud
because shortly after posting I was able to instantiate an external
primitive with user defined code by actually reading the manual.

Thanks to Guy for the presentation. I replicated the example in slide 43.

It looks like this example is intended to be simulated but I don't think the
defined logic function is recognized in MyHDL. The same VHDL file and the
same "ToVHDLWarning: Port is not used: O" is generated if the logic function
is replaced with "pass". In
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#user-defined-code
it says "...conversion of the ..... function is bypassed..."

I think this topic is important. MyHDL is attractive for algorithm
development (my personal interest) but I don't see how it could possibly be
considered for development of a whole fpga project where it controls the top
level module. It is vital to be able to readily use not only chip primitives
but also soft IP cores generated by the chip vendor's tool suite, and it
can't be relied on that everyone involved will know Python.

Is it possible to have a wrapper function for the user-defined code feature
along the lines of:

module_inst = include('module_file.v/.vhd', signal_list,  property_list=None)

If a module is given it can be parsed for signal types and have the signal
names (given as a strings maybe in a list) assigned to these in sequence.
Properties would be needed if an instantiation template has to be given
where a module is not available. module_inst is a dummy generator function
containing a set of signal.read/driven assignments and the user code
assignment (which, vitally, appears to work inside the function but I don't
understand why)

It does not look too ambitious to parse a module for the external signals,
but I don't know enough about the syntax. I was going to attempt something
very basic from looking at sample files.

Comments welcome. What are other's assessments of MyHDL?

Regards

Mike