Re: [myhdl-list] Using existing HDL modules

[Jan C. <jen...@mu...>]

On 03/11/14 14:59, Mike Gill wrote:
> Hi
>
> How do you access chip primitives and hard IP blocks in MyHDL? The chip
> vendor supplies modules and instantiation templates in Verilog or VHDL. Is
> there any way of including or importing these without having to edit the
> Verilog or VHDL file generated by MyHDL? I can't work out whether the
> user-defined code facility can do this.
I have a MyHDL RAM (model?) with content initialisation code which 
simulates in MyHDL and is accepted by the Lattice (Ex Silicon Blue) 
toolchain.

This puts the RAM image into Verilog defparam statements in MyHDL 
user-defined code for the synth tools, and initialises the MyHDL 
RAM model for simulation.

AFAICT the same technique will allow direct access to the all of 
chip primitives.   Haven't looked at IP blocks.

Let me know if you'd like me to send or post code.

Jan Combs.