Re: [myhdl-list] Using existing HDL modules

[Henry G. <he...@ca...>]

On 04/11/14 07:42, Guy Eschemann wrote:
> what this means is that you cannot generate VHDL code that is
> parameterizable using VHDL generics (think of a FIFO that has a "depth"
> generic for example). The parametrization has to be done in MyHDL before
> the actual VHDL code is generated.
Oh, I understand - so you mean you can't pass around a parameterizable 
v* block for others to use. Not as problematic as I interpreted your 
point as being. :)

Cheers,

Henry