Re: [myhdl-list] Using existing HDL modules

[Guy E. <gu...@no...>]

Hello Henry,

what this means is that you cannot generate VHDL code that is 
parameterizable using VHDL generics (think of a FIFO that has a "depth" 
generic for example). The parametrization has to be done in MyHDL before 
the actual VHDL code is generated.

As far as I know, this limitation applies to all all high-level design 
solutions (C-based HLS, Bluespec SV, etc.). It may or may not be an 
issue for you.

Regards,
Guy.

Am 03.11.2014 19:04, schrieb Henry Gomersall:
> On 03/11/14 17:52, Guy Eschemann wrote:
>> I have an example showing how to instantiate an IBUFDS component from
>> the Xilinx Unisim library with user-defined code. You'll find it on
>> the slide number 43 of my presentation on "FPGA Design with Python and
>> MyHDL"
>> (http://www.slideshare.net/GuyEschemann/2014-all-programmabe-days-fpga-design-with-python).
> Hi Guy, that's a great presentation.
>
> One question though: you say on page 45 that MyHDL cannot generate
> parameterizable HDL. What do you mean by this?
>
> My understanding is that with the flexibility of python, parameterizable
> HDL (or indeed almost any kind of metaprogramming niceness) is a
> wonderful thing to be doing with MyHDL. Have I missed something?
>
> Cheers,
>
> Henry
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

-- 
Guy Eschemann
FPGA Consultant, CEO
noasic GmbH
Auenheimer Str. 26a
77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
Mobile: +49 (0) 173 72 51 886
gu...@no...
Follow me on Twitter: @geschema
http://noasic.com
http://fpga-news.de
USt-IdNr.: DE296246015
HRB 711881, Amtsgericht Freiburg i. Br.