Re: [myhdl-list] Using existing HDL modules

[Christopher F. <chr...@gm...>]

On 11/3/2014 12:04 PM, Henry Gomersall wrote:
> On 03/11/14 17:52, Guy Eschemann wrote:
>> I have an example showing how to instantiate an IBUFDS component from
>> the Xilinx Unisim library with user-defined code. You'll find it on
>> the slide number 43 of my presentation on "FPGA Design with Python and
>> MyHDL"
>> (http://www.slideshare.net/GuyEschemann/2014-all-programmabe-days-fpga-design-with-python).
>
> Hi Guy, that's a great presentation.
>
> One question though: you say on page 45 that MyHDL cannot generate
> parameterizable HDL. What do you mean by this?
>
> My understanding is that with the flexibility of python, parameterizable
> HDL (or indeed almost any kind of metaprogramming niceness) is a
> wonderful thing to be doing with MyHDL. Have I missed something?
>
> Cheers,
>
> Henry
>

The HDL in Python (the MyHDL) is very parameterizable,
modular, scalable, etc.  But the generated Verilog/VHDL
is not.  The generated Verilog/VHDL is an convenient
intermediate format.

Hope that helps,
Chris