Re: [myhdl-list] Using existing HDL modules

[Guy E. <guy...@gm...>]

Hello Mike,

I have an example showing how to instantiate an IBUFDS component from the
Xilinx Unisim library with user-defined code. You'll find it on the slide
number 43 of my presentation on "FPGA Design with Python and MyHDL" (
http://www.slideshare.net/GuyEschemann/2014-all-programmabe-days-fpga-design-with-python
).

Hope this helps,
Guy.


Guy Eschemann
FPGA Consultant, CEO
noasic GmbH
Sundheimer Feld 6
77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
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On Mon, Nov 3, 2014 at 3:59 PM, Mike Gill <mj...@gi...> wrote:

> Hi
>
> How do you access chip primitives and hard IP blocks in MyHDL? The chip
> vendor supplies modules and instantiation templates in Verilog or VHDL. Is
> there any way of including or importing these without having to edit the
> Verilog or VHDL file generated by MyHDL? I can't work out whether the
> user-defined code facility can do this.
>
> My knowledge of Verilog and VHDL is very limited.
>
> Many thanks
>
> Mike
>
>
>
>
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