Re: [myhdl-list] Using existing HDL modules

[Christopher F. <chr...@gm...>]

On 11/3/2014 8:59 AM, Mike Gill wrote:
> Hi
>
> How do you access chip primitives and hard IP blocks in MyHDL? The chip
> vendor supplies modules and instantiation templates in Verilog or VHDL. Is
> there any way of including or importing these without having to edit the
> Verilog or VHDL file generated by MyHDL? I can't work out whether the
> user-defined code facility can do this.
>
> My knowledge of Verilog and VHDL is very limited.
>
> Many thanks
>
> Mike
>

In short, user-defined code is used to instantiate
third party IP provided in Verilog of VHDL (including
hard IP).  For simulation you will need to created
a functional model or co-simulate with existing V*
models.

http://docs.myhdl.org/en/latest/manual/conversion.html#user-defined-code

Regards,
Chris