[myhdl-list] time unit in cosimulation

[Shen C. <she...@co...>]

 

Hi All, 

In our experiment of using MyHDL in an SRAM BIST design,
we used the following flow: 

myHDL RTL and testbench -> convert to
verilog rtl -> Synthesis/Place&Route -> co-simulation of myHDL testbench
with the sdf back-annotated verilog. 

Only the design (BIST module) is
converted to verilog, the SRAM is considered as a part of the testbench,
and is modeled behaviorally. 

This allows us to model some complex
fault modes in the SRAM. 

In the co-simulation phase, we realized that
the time in myHDL is 1000x that in verilog. 

It may be fine if verilog
uses `timescale 1ns/1ps, and myHDL uses 1ns time step. 

However, some
of the fault modes in SRAM requires higher timing precision, so we went
for 1ps time step in myHDL. 

It took us quite some time to figure out
that, in this case, we need to tell the verilog simulator to use 1 fs
time step. 

Only after finding this out by trial and error, did I
realize that the manual mentioned this 1000x factor for delta cycle
implementation. 

A coarse reading of the vpi source code confirmed
this. 

I hope the manual can explain the implication of the 1000x
factor from the users' perspective, hopefully saving users some time.


regards,
shenchen 

-- 

SHEN Chen General
Manager
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Cogenda Co Ltd
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