Re: [myhdl-list] subtype RamWord_t

[Christopher F. <chr...@gm...>]

There is no method to define a type for the generated
VHDL.  The generator will not create types in VHDL,
if you are integrating existing VHDL components with
MyHDL generated VHDL components you will need to use
conversion functions in the VHDL.

If you are having issues on the VHDL side, you can
post the VHDL code and someone might be able to help
or try one of the VHDL specific groups.

Regards,
Chris

On 10/2/2014 2:38 PM, Edward Vidal wrote:
> Hello all,
> In the process of learning myhdl and trying to convert a vdh code snippet to myhdl.
> RAM_WIDTH_C = 16 is defined as constant
>
> subtype RamWord_t is unsigned(RAM_WIDTH_C-1 downto 0);  -- RAM word type.
>
>
> RAM_SIZE_C = 16384
> For addr I used
>
> addr_r = addr_r = Signal(intbv(0, min = 0, max = RAM_SIZE_C))
>
> which converted  addr_r: out unsigned(13 downto 0); which
> I am trying dataToRam_r = Signal(intbv(0, min = 0, max = 2**RAM_WIDTH_C - 1))
> which is correct I think but not of subtype RamWord_t
> dataToRam_r: out unsigned(15 downto 0);
>
> What is the process to make it of type RamWord_t
> Any and all help is appreciated.
>
> Edward Vidal Jr.
> e-mail dev...@sb...
> 915-595-1613
>
>
>
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