[myhdl-list] Result of 17-bit expression is truncated to fit in 16-bit target.

[Edward V. <dev...@sb...>]

Hello all,
I generated a Verilog file with myhdl (see below).  The jpeg.v, top_level_mod.vhd, and VHDL_LIB
generates a bit file with ISE 14.7.
I am running on XulA2-LX9 from XESS sending the flags even_odd_s & fwd_inv_s to the FPGA.
I am sending back from the FPGA res_s  left_s sam_s  right_s, which are being read from SDram
even_odd_s fwd_inv_s res_s  left_s sam_s  right_s 
1                   1        2  0x0002 0x00a3 0x00a0 0x009b
1                   0    318  0x013e 0x00a3 0x00a0 0x009b
0                   0      80  0x0050 0x00a3 0x00a0 0x009b
0                   1    240  0x00f0 0x00a3 0x00a0 0x009b
The res_s is computed on PC with Python and compares with the returned res_s values.
I am currently having problems saving res_s to SDram.  I am getting the following warnings. 

WARNING:HDLCompiler:413 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\fast_clk_jpeg\jpeg.v"
Line 50: Result of 17-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\fast_clk_jpeg\jpeg.v"
Line 53: Result of 17-bit expression is truncated to fit in 16-bit target.
output signed [15:0] res_s;
reg signed [15:0] res_s;

The lines producing the warnings are the following.
res_s <= (sam_s + $signed(((left_s + right_s) + 2) >>> 2));  line 50
res_s <= (sam_s - $signed(((left_s + right_s) + 2) >>> 2));  line 53

When I try to make the res_s 17 bit my code will not Synthesize.
The code worked with the jpeg.vhd but works better with jpeg.v.
I appreciate any and all help.
Thanks
Edward Vidal Jr.
// File: jpeg.v
// Generated by MyHDL 0.9dev
// Date: Sat Sep 20 01:39:13 2014


`timescale 1ns/10ps

module jpeg (
    clk_fast,
    left_s,
    right_s,
    sam_s,
    res_s,
    even_odd_s,
    fwd_inv_s,
    updated_s,
    noupdate_s
);


input clk_fast;
input signed [15:0] left_s;
input signed [15:0] right_s;
input signed [15:0] sam_s;
output signed [15:0] res_s;
reg signed [15:0] res_s;
input even_odd_s;
input fwd_inv_s;
input updated_s;
output noupdate_s;
reg noupdate_s;






always @(posedge clk_fast) begin: JPEG_HDL
    if (updated_s) begin
        if (even_odd_s) begin
            if (fwd_inv_s) begin
                res_s <= (sam_s - ($signed(left_s >>> 1) + $signed(right_s >>> 1)));
            end
            else begin
                res_s <= (sam_s + ($signed(left_s >>> 1) + $signed(right_s >>> 1)));
            end
        end
        else begin
            if (fwd_inv_s) begin
                res_s <= (sam_s + $signed(((left_s + right_s) + 2) >>> 2));
            end
            else begin
                res_s <= (sam_s - $signed(((left_s + right_s) + 2) >>> 2));
            end
        end
    end
    else begin
        noupdate_s <= 1;
    end
end

endmodule


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613