[myhdl-list] fsm.v and fsm.vhd

[Edward V. <dev...@sb...>]

Hello all,
I am new to HDL and myhdl.  I am using Xilinx ISE 14.7.  I created a simple FSM with myhdl.  When I add the "RamCtrl.v" file.   I can create a "TB.vhd"   file and run a simulation with no problems.  


When I try with  "RamCtrl.vhd",  I also add "pck_myhd_09.vhd".  I can Synthesize, Implement Design, and  Generate Programming File no problems.   When I create a "TB.vhd" and try run the simulation I get the following errors.
  ERROR:HDLCompiler:377 - "C:/Xilinx/14.7/ISE_DS/fsm_test1/TB.vhd" Line 45: Entity port state does not match with type std_logic of component port
ERROR:HDLCompiler:377 - "C:/Xilinx/14.7/ISE_DS/fsm_test1/TB.vhd" Line 49: Entity port addrsam_r does not match with type std_logic_vector of component port
ERROR:HDLCompiler:377 - "C:/Xilinx/14.7/ISE_DS/fsm_test1/TB.vhd" Line 50: Entity port addrjpeg_r does not match with type std_logic_vector of component port
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit tb in library work failed

I believe the problem is related to the "RamCtrl.vhd" has the following.
 attribute enum_encoding: string;

    type t_enum_t_State_1 is (
    INIT,
    RD_AND_JPEG_DATA,
    WR_DATA,
    INTERLACE,
    DONE
);
attribute enum_encoding of t_enum_t_State_1: type is "00001 00010 00100 01000 10000";

 How do you fix the problem in the "TB.vhd" file this missing causes errors in other signals.
I appreciate all the help.
Thanks 


Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613