Re: [myhdl-list] Mismatch between Simulation and Conversion

[Jan D. <ja...@ja...>]

On 09/13/2014 06:07 PM, Josy Boelen wrote:

> Can I classify this a bug? Or is it just me (not reading the manual
> thoroughly enough)?

It's really quite simple. When conversions succeeds, and there
is a mismatch between MyHDL and Verilog/VHDL simulation, then
there is a bug. No excuses.

Any rule has exceptions - the exception here is start-up
and initialization behavior at time 0.

Jan

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