[myhdl-list] Mismatch between Simulation and Conversion

[Josy B. <jos...@gm...>]

Hi all,

In a large project (6700 lines of generated VHDL) I created a counter:
#start of code
def addresscounter( clk, reset, startValue, Length , initP, cntEn, isStart, 
isEnd, Q, WRAP_AROUND = False ):

   lq = Signal(intbv(0)[len(Q):])

   if WRAP_AROUND == False:
      @always_seq(clk.posedge, reset=reset)
      def counter():
         endval = startValue + Length
         if initP or cntEn:
            if initP :
               lq.next = startValue
               isStart.next = 1
               isEnd.next = 0
            else:
               isStart.next = 0
               if lq < (endval - 1):
                  lq.next = lq + 1

               if lq == (endval - 2) or lq == (endval - 1):
                  isEnd.next = 1
               else:
                  isEnd.next = 0

...
#end of code
The project simulated fine, but didn't run in the FPGA because the converted 
VHDL:
-- start of VHDL
entity addresscounter is
	port(
		clk        : in  std_logic;
		reset      : in  std_logic;
		startValue : in  unsigned(7 downto 0);
		Length     : in  unsigned(7 downto 0);
		initP      : in  std_logic;
		cntEn      : in  std_logic;
		isStart    : out std_logic;
		isEnd      : out std_logic;
		Q          : out unsigned(7 downto 0)
	);
end entity addresscounter;

architecture MyHDL of addresscounter is
	signal lq : unsigned(7 downto 0);

begin
	ADDRESSCOUNTER_COUNTER : process(clk, reset) is
		variable endval : integer;
	begin
		if (reset = '1') then
			isEnd   <= '0';
			isStart <= '0';
			lq      <= to_unsigned(0, 8);
		elsif rising_edge(clk) then
			endval := to_integer(startValue + Length);
			if (bool(initP) or bool(cntEn)) then
				if bool(initP) then
					lq      <= startValue;
					isStart <= '1';
					isEnd   <= '0';
				else
					if (signed(resize(lq, 9)) < (endval 
- 1)) then
						lq      <= (lq + 1);
						isStart <= '0';
					else
						lq      <= startValue;
						isStart <= '1';
					end if;
					if (signed(resize(lq, 9)) = (endval 
- 2)) then
						isEnd <= '1';
					else
						isEnd <= '0';
					end if;
				end if;
			end if;
		end if;
	end process ADDRESSCOUNTER_COUNTER;

	Q <= lq;

end architecture MyHDL;
--end of VHDL

The offending line is:
	endval := to_integer(startValue + Length);

as both StartValue and Length are unsigned(7 downto 0), the operation 
(startValue + Length) wraps around to zero in VHDL, but not when simulating 
in MyHDL.

Can I classify this a bug? Or is it just me (not reading the manual 
thoroughly enough)?

Best regards,

Josy