[myhdl-list] Possible Bug

[Daryl W. <dw...@ou...>]

Hello everyone,
While using MyHDL today, I am fairly certain that I came across a bug. At least, it didn't operate as I had expected. Please, correct me if I am mistaken and this is unsupported. I made some mockup code to demonstrate the problem Here it is:''' START OF CODE '''from myhdl import *
def add_c(inp_value, outp_value, clock):	''' '''	MY_CONSTANT = long(1234)	temp_sum = Signal(intbv(0)[16:])
	@always(clock)	def logic():		if inp_value > MY_CONSTANT:			temp_sum.next = MY_CONSTANT		else:			temp_sum.next = inp_value		outp_value.next = temp_sum + MY_CONSTANT
	return logic
if __name__ == '__main__':	a = Signal(intbv(0)[16:])	b = Signal(intbv(0)[16:])	clock = Signal(False)	toVHDL(add_c, a, b, clock)
''' END OF CODE '''
After toVHDL() conversion, I obtained the following (with whitespace edited to improve readability):
-- START OF CODE-- File: add_c.vhd-- Generated by MyHDL 0.8-- Date: Tue Sep  2 18:20:45 2014
library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;use std.textio.all;
use work.pck_myhdl_08.all;
entity add_c is    port (        inp_value: in unsigned(15 downto 0);        outp_value: out unsigned(15 downto 0);        clock: in std_logic    );end entity add_c;
architecture MyHDL of add_c issignal temp_sum: unsigned(15 downto 0);begin
ADD_C_LOGIC: process (clock) isbegin    if (inp_value > 1234) then        temp_sum <= to_unsigned(MY_CONSTANT, 16);    else        temp_sum <= inp_value;    end if;    outp_value <= (temp_sum + 1234);end process ADD_C_LOGIC;
end architecture MyHDL;-- END OF CODE
The problem: MY_CONSTANT is used as a named constant in the RTL, but it was not declared in the declarative region. It seems that constants of type long are not recognized as constants and are not declared in the declarative region by toVHDL(). The same example using an int instead of a long works fine in simulation and conversion. I was using a long in my code because the value was 48 bits wide.
For the time being, a workaround is to use a temporary variable in the RTL. In other words replace the line "temp_sum.next = MY_CONSTANT" with the following two lines:''' START CODE '''temp_var = MY_CONSTANTtemp_sum.next = temp_var''' END CODE'''This converts the MY_CONSTANT to its numeric value and the converted code still simulates correctly. 
I tested this with MyHDL versions 0.8 and 0.9dev.
Is the mailing list the proper forum for reporting this or is there a better place?
Thanks,Daryl