Re: [myhdl-list] High-level thinking: Using Python for rapid verification

[Christopher F. <chr...@gm...>]

On 7/31/2014 12:46 PM, Colin Beighley wrote:
> Looks cool. Correct me if I'm wrong, but there's currently not a great way
> to integrate existing Verilog/VHDL IP into MyHDL simulations, is there?
> Seems like this could bridge that gap nicely.
>

Yes, there are options to integrate 3rd IP in MyHDL
just not lots of examples.  We had a discussion just
the other day how to do so in one case - is there a
disgestible example that you can think of that might
help make this clear?

I guess it depends on how you define "nicely" and it
might be worthwhile determining if there are features
that can be leveraged (V* signal extraction, etc.).

Regards,
Chris

>
> On Thu, Jul 31, 2014 at 9:17 AM, Christopher Felton <chr...@gm...>
> wrote:
>
>> Has anyone else watched this webinar?  I was curious of
>> others thoughts?
>>
>> https://www.aldec.com/en/support/resources/multimedia/webinars/1774
>> (note you have to create a user account etc. to view
>> the webinar).
>>
>> Would anyone be interested in determining if some of the
>> backend code can be merged into MyHDL?  Specifically the
>> VHPI (which will be hard to test without a VHPI simulator)
>> and the VPI code that extracts the hierarchy from lower
>> HDL?  It would not be directly usable but it might be a
>> starting point.
>>
>> Regards,
>> Chris
>>
>>
>>
>>
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