Re: [myhdl-list] Pre-Init RAM

[Jan C. <jen...@mu...>]

On 24/07/14 08:53, Martin Strubel wrote:
> There is so much case dependency, that it might be very hard to satisfy
> everyone. I'd rather see if we can collect a few use cases and tricks
> from the community and document them.
I have a user defined code solution for the Lattice (ex Silicon 
Blue) tiny low power iCE40 FPGA parts.

Custom tools write a RAM image file containing the initialisation 
data.   This file contains a sixteen item list of 256b intbv, which 
is close to the format required in Verilog or VHDL instantiations 
of the block RAM primitive.  Inside a python comment there is also 
a simple hex dump so that I can read the content, because the bit 
ordering of the initialisation data is unsuitable for me to read.

The design imports this file and the RAM definition, which is 
instantiated with the initialisation data.  The initialised RAM 
works in simulation, and incorporates user-defined Verilog or VHDL 
code suitable to pass the initialisation data to the synthesis 
tools as Verilog defparam statements, or a VHDL generic map( statement.

If anyone else wants to use this I will try to complete testing and 
documenting soon.  Otherwise it will be much later.

Jan Coombs.
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