Re: [myhdl-list] Pre-Init RAM

[Daryl W. <dw...@ou...>]

If it is desired by more people to have an option to turn on/off signal initializations and list of signal initializations, I might be willing to work on writing tests and code for it and submit a patch. I'd like to hear more feedback first though on whether other people might find this useful. It'll be a little work as I'm a little rusty in Verilog (although this seems like it should be pretty straightforward). My current strategy is working very well for me right now. So, if no one else thinks it will be useful for them, then probably not worth the effort.
The page linked by the page you sent says that there is no need that the synthesis tools do anything meaningful with the initialization code and that it is primarily to make the pre- and post-conversion simulations match. Doesn't that mean that having an option to turn it on/off should be available regardless of synthesis results? I would envision a way to activate an individual signal or signal list. Possibly, this could be accomplished by way of an attribute called "._initialize" that defaults to False, but can be set to True in the constructor using a keyword argument. This would allow everyone to carry on like normal, but it would also enable the initializations for those who want to use them. 
-Daryl