Re: [myhdl-list] Pre-Init RAM

[Christopher F. <chr...@gm...>]

On 7/21/14 4:50 PM, Daryl Wasden wrote:

>
> http://article.gmane.org/gmane.comp.python.myhdl/2235
>
> Its a long thread with lots of discussion. The use-case for converting
> initial values that I find most interesting is the pre-init RAM for
> FPGAs. I have used this extensively with xst and VHDL. I often use an
> array of signed numbers for storing filter coefficients, twiddle factors
> for FFTs, and other quantities. Sometimes, I want these things to be
> modifiable at run-time (which prevents me from using the case
> structure/tuple of ints method). I prefer to write it into my RTL,
> because it allows the synthesis tool to choose between block RAM,
> distributed RAM, etc. for me. Unless I have a compelling reason to worry
> about these low level details, I'd rather not.

Code exists to enable initial values but the difficult
part has been making sure support is consistent across
synthesis vendors (mainly FPGA).  Since we have not had
someone willing to test all the vendors and verify the
generic approach we have not been able to turn it on.

The latest information on the initial value support can be
found here (this is probably a little outdated):
http://dev.myhdl.org/ideas/initial-values.html

The previous does not require a separate function call but
will use the initial value in the declaration (instantiation)
as the init value.

Maybe we need a hook to provide people with there own approach.
One such hook is using the "user defined" modules.  This way
you can write whatever VHDL you need to generate the initial
values.  This might be the best option until we know the
generic method is supported by "most" tools.

Regards,
Chris