[myhdl-list] Pre-Init RAM

[Daryl W. <dw...@ou...>]

Hello everyone,
I do a lot of signal processing blocks for prototyping in FPGAs. I love MyHDL and prefer to use it whenever possible. That said, I was looking for a solution to a problem I am having. There is a thread dating back to 2012 where there was a discussion regarding the conversion of initial values to VHDL and Verilog. See the link below for more information:
http://article.gmane.org/gmane.comp.python.myhdl/2235

Its a long thread with lots of discussion. The use-case for converting initial values that I find most interesting is the pre-init RAM for FPGAs. I have used this extensively with xst and VHDL. I often use an array of signed numbers for storing filter coefficients, twiddle factors for FFTs, and other quantities. Sometimes, I want these things to be modifiable at run-time (which prevents me from using the case structure/tuple of ints method). I prefer to write it into my RTL, because it allows the synthesis tool to choose between block RAM, distributed RAM, etc. for me. Unless I have a compelling reason to worry about these low level details, I'd rather not. 
I have created a contrived test module and something I wrote quickly to demonstrate one approach to solving this issue on my own. This example is highly contrived, but it illustrates how to initialize signals, and I think it probably wouldn't be too hard to convert it to support Verilog.
You can download the example here: 
https://bitbucket.org/dwasden/myhdl_util
Line 226-234 demonstrate the interface for a new function, initVHDL() that has the same arguments as toVHDL(). I ran the code with the 0.9dev branch installed. 
To summarize the approach: A call is made to the toVHDL() function on the test module to produce testmod.vhd (provided in the repository so you don't need to run the code). Then, a call is made to the initVHDL() function. The call to initVHDL() extracts the hierarchy, then generates the signal and memory lists using the same internal functionality as toVHDL(). Then it proceeds line by line through the VHDL file and tries to find lines that match Signal declaration syntax. If a line doesn't match, it repeats it. If a line matches, it searches for the signals in the signal and memory lists. If the signals are found, it writes a signal declaration with an initial value equal to the value of the signal in the signal list. It may be a good idea to do this more selectively in the future if I continue to need it (for example, only for signal names that are explicitly passed to the function). 
I don't like this approach primarily because I am using the converter's internal functionality to find the signal names and initial values. This functionality is not part of the public API and may change in future releases, but I also don't see a better way to achieve the results that I want (automated signal initialization to match the VHDL output and the MyHDL output). I haven't yet found anything in the documentation, and the closest thing I found was that thread. 
So, this leaves me wondering... Is there already support for this in MyHDL? If not, does anyone else think that this feature would benefit them? Is it something that the community would be supportive of?
Thanks,Daryl
Warning: the code in the repository has been lightly validated. It is for illustration of the method only. If I were to provide something for the general public to use, then I would test it much more thoroughly (and provide test code for anyone else to run so they could modify it for their own uses).