[myhdl-list] Best way to think in test driven development using MyHDL coming from VHDL?

[André P. <and...@gm...>]

So, I am having really fun with MyHDL but I think I am testing things in
the wrong way.

I am toying around with my Cordic module (that I got working thanks to your
help) and I am trying to evolute my test bench

http://pastebin.com/Hbd9eRui

Is this the best way to do it?

I am evaluation it by running:

py.test tb_cordic.py -v

It does work but I don't know if it's the best way to do it,

I also have two functions doing almost the same thing, (random_bench and
fft_bench), this violates the DRY mantra, but I could'nt find a way to do
it generic enough.

Taking all the DRY stuff (that also appears on my tests) that I messed up
while testing, any good tips? Am I in the right path?

I would like py.test to print what it is doing, like, when it runs
test_max_clock it should print the clk periods that he is going throught,
print statement do not work in py.test, only when an assert fails

I would also be glad if someone could point me to a good book in this
subject (doesn't need to be myhdl or python related)

Cheers and thanks for the great work! It's so much better than looking at
waveforms...





-- 
Atenciosamente/Regards
André Castelan Prado