Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Jan C. <jen...@mu...>]

On 12/07/14 09:58, Jan Decaluwe wrote:
> On 07/11/2014 11:12 AM, Jan Coombs wrote:
>
>> Yesterday I found that the need for [:] in variable assignments is
>> demonstrated in two of the 'learning by example' code samples, so
>> hopefully no-one else will get to see my pain.
> The primary reference should be the manual.
> These issues are explained in depth:
>
> http://docs.myhdl.org/en/latest/manual/conversion.html#assignment-issues
>
Not complaining, but 10/12 the way through the manual, in  a 
section about conversion


I'm very happy now, because I just re-wrote this code with a 
variable and it now works:

   @always_seq(clk.posedge, reset=rst)
   def irLogic():
     ''' load ir '''
     nextIR = intbv(0)[GSW*2:]
     nextIR[:] = ir
     if   (irState==IRstate.IrA):
       nextIR[GSW*2:GSW] = db01Data
       nextIR[GSW:0] = 0
     elif (irState==IRstate.IrB):
       nextIR[GSW:0] = db01Data
     ir.next = nextIR


I can probably now guess why the old code silently failed, but it 
was frustrating, and sapped my interest:

   @always_seq(clk.posedge, reset=rst)
   def irLogic():
     ''' load ir '''
     if   (irState==IRstate.IrA):
       ir[GSW*2:GSW].next = db01Data  #WHYNOT?
       ir[GSW:0].next = 0             #WHYNOT?
       #ir.next = db01Data<<GSW
     elif (irState==IRstate.IrB):
       ir[GSW:0].next = db01Data      #WHYNOT?
       #ir.next = ir|db01Data


Thanks for your help, I'll hijack this thread no further, Jan Coombs
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