Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

So, here I am. Finally had some time to finish it;

It's working perfectly! Here is my Py cordic code:
http://pastebin.com/NzphEmrY and here is my testbench in Py:
http://pastebin.com/PtqKWJN6
I do have a problem with the angle validation, The py function returns from
-pi to pi and I have to do the same with my cordic, but I won't worry about
that now.

So, I've generated the VHDL and compiled in my project, here is the VHDL:
http://pastebin.com/5j5muvGq

Compared to my OLD VHDL ( http://pastebin.com/v9FJVUXr ), I do prefer the
generated one, it uses less logic, the ports are smaller and it's also 1 uS
faster (and I have python functions, yay). This OLD VHDL is really old,
there are a few errors with it like mixing numeric_std and signed_artih,
but...

the MyHDL VHDL isn't working in my product! :(

I know that's a lot of work, but I've been scratching my head and I can't
find why the MyHDL VHDL isn't working. I am getting some random values from
my acquisition board instead of the right mag/ang pair.

I've made a test bench with both VHDLs running in paralalel and I get the
same result from both.

I don't know if it's a problem with the Variable usage or these cases
returning a constant to a variable, or even the state machine being half
if/else half case. Everything seems OK, I took a look at the RTL Viewer and
didn't see anything strange.


Cheers




On Fri, Jul 4, 2014 at 1:10 PM, André Prado <and...@gm...> wrote:

> Thanks again.
>
> Well, even if the synthesis result is the same, I really need to use the
> CASE statement for state machines. If I don't do it the product leader
> won't let me use MyHDL, lol :-)
> Also, we use this here:
>
> attribute SYN_ENCODING of READ_PARAMETER_ST_TYPE : type is "safe";
>
> As far as I understood, I can send this line directly to the VHDL with the
> special MyHDL command vhdl_code, right?
>
>
>
> Cheers
>
>
> On Fri, Jul 4, 2014 at 11:59 AM, Christopher Felton <
> chr...@gm...> wrote:
>
>> On Fri, Jul 4, 2014 at 9:43 AM, André Prado <and...@gm...>
>> wrote:
>>
>>> Humm, my state machine was translated to an IF else if fashiong instead
>>> of switch case.
>>>
>>
>> Thats fine, compare synthesis results if there is concern.
>>
>> Regards,
>> Chris
>>
>>
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>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>



-- 
Atenciosamente/Regards
André Castelan Prado