Re: [myhdl-list] Problem converting list of intbv

[Christopher F. <chr...@gm...>]

On 7/8/14 5:07 AM, Pedro Pedruzzi wrote:
> Guy, thanks for your response.
>
> Unfortunately I can't use tuples because I acually write to the "array"
> as well. So allow me to modify my example. Now I have 4 counters and the
> one selected with signal s will get incremented and tranfered to the output.
>
> Shouldn't list of intbvs be supported?

Yes, a tuple of intbv, and int is supported from ROM,
if you want to RAM you need a list-of-signals,
change your u32 function to:

     def u32(val = 0):
         return Signal(uint(32, val))

In addition, move your RAM definition (I know if this
case it won't be synthesized using a BRAM because it is
small but it act as RAM) to the elaboration phase:

def mux(s, o):
     i = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb),
           u32(0xcccccccc), u32(0xdddddddd) ]
     @always_comb
     def logic():
         o.next = i[s]
     return logi


Also see,
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#ram-inference

Personally I don't like the use of functions in this
case.  You remove modularity from you module and I
don't think it adds to readability,  I would simplify
to something like:

     def mux(s, o, width=32):
         i = [ Signal(intbv(val)[width:])
               for val in (0xaaaaaaaa, 0xbbbbbbbb,
                           0xcccccccc, 0xdddddddd,) ]
         @always_comb
         def logic():
             o.next = i[s]
     return logic


Regards,
Chris

>
> from myhdl import Signal, always_comb, intbv, toVerilog
>
> def uint(width, val = 0):
>      return intbv(val, 0, 2 ** width)
>
> def u32(val = 0):
>      return uint(32, val)
>
> def counters(s, o):
>      m = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb), u32(0xcccccccc),
> u32(0xdddddddd) ]
>      @always_comb
>      def logic():
>          m[s] += 1
>          o.next = m[s]
>      return logic
>
> s = Signal(intbv(0)[2:])
> o = Signal(intbv(0)[32:])
>
> toVerilog(counters, s, o)
>
> ızznɹpǝԀ oɹpǝԀ
>
>
> On Tue, Jul 8, 2014 at 5:46 AM, Guy Eschemann <gu...@no...
> <mailto:gu...@no...>> wrote:
>
>     Hello Pedro,
>
>     here's how I would do it:
>
>     def mux(s, o):
>          i = (0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0xdddddddd)
>
>
>     @always_comb
>     def logic():
>              o.next = i[s]
>     return logic
>
>     Regards,
>     Guy.
>
>     On Jul 8, 2014, at 1:16 AM, Pedro Pedruzzi wrote:
>
>>     Hello,
>>
>>     I am new to this list.
>>
>>     I am getting the following exception while trying to convert a
>>     simple mux to Verilog.
>>
>>     myhdl.ConversionError: in file list-of-intbv.py, line 12: Not
>>     supported: list
>>
>>     I know I could use tuple of int (since I am using constants), but
>>     I want to use lists to implement array of registers and the docs
>>     says it is possible.
>>
>>     Here is the design:
>>
>>     from myhdl import Signal, always_comb, intbv, toVerilog
>>
>>     def uint(width, val = 0):
>>         return intbv(val, 0, 2 ** width)
>>
>>     def u32(val = 0):
>>         return uint(32, val)
>>
>>     def mux(s, o):
>>         @always_comb
>>         def logic():
>>             i = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb), u32(0xcccccccc),
>>     u32(0xdddddddd) ]
>>             o.next = i[s]
>>         return logic
>>
>>     s = Signal(intbv(0)[2:])
>>     o = Signal(intbv(0)[32:])
>>
>>     toVerilog(mux, s, o)
>>
>>
>>     Any help is appreciated. Thanks.
>>
>>     ızznɹpǝԀ oɹpǝԀ
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