Re: [myhdl-list] Verilog RAM

[Christopher F. <chr...@gm...>]

On 7/7/14 4:55 PM, Edward Vidal wrote:
> Hello,
> I am new to myhdl and python.  I have been able to create ram_l and
> ram_r. I have been able to also create a testbench that is sort of
> working.  I also have a ram_odd where the result of
>      @always(clk.posedge)
>      def hdl():
>
>          pix.din_odd.next = (pix.dout_l + pix.dout_r)*ca1
>
>      return hdl
> When n = 1 I would like to use pix.dout_odd -1and pix.dout_odd +1
> instead of what I have now.

What is "n" (haven't looked at the attached code yet,
probably won't have time to work through it).

You can always conditionally created the myhdl-generators

     if n == 1
	@always(clk.posedge)
	def hdl():
	    pix.din_odd.next = (pix.dout_l - pix.dout_r) * cal
     else:
        @always(clk.posedge)
	def hdl():
	    pix.din_odd.next = (pix.dout_l + pix.dout_r) * cal

Or you can include the condition in generator.

Regards,
Chris