[myhdl-list] Verilog RAM

[Edward V. <dev...@sb...>]

Hello,
I am new to myhdl and python.  I have been able to create ram_l and ram_r. I have been able to also create a testbench that is sort of working.  I also have a ram_odd where the result of 

    @always(clk.posedge)
    def hdl():
                 
        pix.din_odd.next = (pix.dout_l + pix.dout_r)*ca1
     
    return hdl
When n = 1 I would like to use pix.dout_odd -1and pix.dout_odd +1 instead of what I have now.  

In the object pix of have methods to set the addr and we lines but don't know how to do the same with the above @always. to not use the ram_l & ram_r. 

    def setSig_we_odd(self,val):   
        self.we_odd.next = Signal(bool(val))
        
    def setSig_we_even(self,val):   
        self.we_even.next = Signal(bool(val))
    
     def setSig_we_l(self,val):   
        self.we_l.next = Signal(bool(val))
    
     def setSig_we_r(self,val):   
        self.we_r.next = Signal(bool(val))
    
     def setSig_addr_odd(self,val):   
        self.addr_odd.next = Signal(intbv(val))

     def setSig_addr_even(self,val):   
        self.addr_even.next = Signal(intbv(val))

    def setSig_addr_l(self,val):   
        self.addr_l.next = Signal(intbv(val))

    def setSig_addr_r(self,val):   
        self.addr_r.next = Signal(intbv(val))

    def setSig_din_odd(self,val):   
        ww = (26,18)
        self.din_odd.next = Signal(fixbv(val)[ww])        

    def setSig_din_l(self,val):   
        ww = (26,18)
        self.din_l.next = Signal(fixbv(val)[ww])

    def setSig_din_r(self,val):
        ww = (26,18)
        self.din_r.next = Signal(fixbv(val)[ww])

 The file attached is what I am using.
I would also like to use the methods in a python model instead of just in the testbench?
Any help will be appreciated.
Thanks
 

Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613