Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Christopher F. <chr...@gm...>]

On Fri, Jul 4, 2014 at 9:21 AM, André Prado <and...@gm...> wrote:

> Now it says
>
> Can't infer variable type: real_reg and the line goes to the declaration
> real_reg = Signal(intbv(....))
> (This is the code with this modification : http://pastebin.com/UFV4Pp84)
>

You have to move the declaration (instantiation) outside of the
@always.


>
> I saw your EDAplayground code, the problem is, I do need to register the
> inputs, looks reasonable to use real_reg as a reg, right?
>
> How MyHDL deals with this? At least, as far as I know, in FPGA designs you
> should register the inputs/outputs of your module for a better throughput
> and fitter possibilities, like Logic Lock from Altera.
>

Using a Signal will add the register - take care it adds it where you
want, you will have considerable logic in front of the reg (selecting
what to load in the real_reg).


Regards,
Chris