Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module
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Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module
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From: André P. <and...@gm...> - 2014-07-04 14:28:30
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Sorry I forgot to put outside the generator, it works now!!! Thank you so much. On Fri, Jul 4, 2014 at 11:22 AM, André Prado <and...@gm...> wrote: > Better FMAX, wrong word. :) > > > On Fri, Jul 4, 2014 at 11:21 AM, André Prado <and...@gm...> > wrote: > >> Now it says >> >> Can't infer variable type: real_reg and the line goes to the declaration >> real_reg = Signal(intbv(....)) >> (This is the code with this modification : http://pastebin.com/UFV4Pp84) >> >> I saw your EDAplayground code, the problem is, I do need to register the >> inputs, looks reasonable to use real_reg as a reg, right? >> >> How MyHDL deals with this? At least, as far as I know, in FPGA designs >> you should register the inputs/outputs of your module for a better >> throughput and fitter possibilities, like Logic Lock from Altera. >> >> Christopher, thank you very much for taking your time to help me with >> this issue. >> >> >> >> >> >> >> >> >> On Fri, Jul 4, 2014 at 10:31 AM, Christopher Felton < >> chr...@gm...> wrote: >> >>> If you convert everything to: >>> >>> real_reg.next = .... >>> >>> then you need to define real_reg as: >>> >>> real_reg = Signal(...) >>> >>> outside the generator, if you leave real_reg as a variable >>> (that is declared inside the generator as real_reg = intbv(...)) >>> then you need to use [:] everywhere. >>> >>> you should be able to access the EDAplayground version now. >>> >>> Hope that helps, >>> Chris >>> >>> >>> On Fri, Jul 4, 2014 at 8:24 AM, André Prado <and...@gm...> >>> wrote: >>> >>>> Thanks Jan, I understand it now. >>>> >>>> Christopher, I made the alterations with your suggestions, however the >>>> same error when I try to convert still happens. >>>> >>>> http://pastebin.com/E2JGAJ50 >>>> >>>> >>>> KeyError: 'real_reg' and a long traceback list error >>>> >>>> Any ideas? >>>> >>>> Also, I cannot access this link: >>>> http://www.edaplayground.com/x/eW >>>> >>>> Says I don't have the permission required. >>>> >>>> Cheers >>>> >>>> >>>> On Fri, Jul 4, 2014 at 9:44 AM, Jan Decaluwe <ja...@ja...> >>>> wrote: >>>> >>>>> On 07/04/2014 02:38 PM, André Prado wrote: >>>>> > I meant that you can't do this in VHDL but I thought that in MyHDL >>>>> you could do that. >>>>> >>>>> http://myhdl.org/start/why.html#signals-and-variables-like-vhdl >>>>> >>>>> > >>>>> > Thanks for the Explanation, I look forward to translate the code of >>>>> my product from VHDL to MyHDL :), still in the learning process but the >>>>> power of Python makes VHDL looks out dated hehe. >>>>> > >>>>> > Cheers >>>>> > >>>>> > >>>>> > On Fri, Jul 4, 2014 at 9:33 AM, Christopher Felton < >>>>> chr...@gm... <mailto:chr...@gm...>> wrote: >>>>> > >>>>> > On Fri, Jul 4, 2014 at 6:50 AM, André Prado < >>>>> and...@gm... <mailto:and...@gm...>> wrote: >>>>> > >>>>> > So, I can't use the same signal as a signal and a variable. >>>>> Just like VHDL :) >>>>> > >>>>> > >>>>> > Not sure what you mean? You can mix the signal assignment >>>>> > and variable assignment in VHDL? If you declare a signal you >>>>> > need to use "<=" if a variable ":=". >>>>> > >>>>> > MyHDL only has one assignment operator, "=". But the types >>>>> > need to match. You need to determine if you really want a signal >>>>> > or a variable: >>>>> > http://www.jandecaluwe.com/hdldesign/signal-assignments.html >>>>> > >>>>> > >>>>> > What is the difference between assigning a value with [:] >>>>> and without it? All the intbv values need a [:] ? >>>>> > >>>>> > >>>>> > In Python everything is a reference >>>>> > >>>>> > x = intbv(0, min=-4, max=4) >>>>> > y = intbv(0, min=-8, max=8) >>>>> > # ... >>>>> > x = 2 >>>>> > y[:] = 4 >>>>> > assert isinstance(x, intbv) # will fail >>>>> > assert isinstance(y, intbv) # will pass >>>>> > >>>>> > The [:] indicates you are updating the value of the intbv type >>>>> > (updating all the bits). If you didn't do this you would loose >>>>> the >>>>> > intbv information, because the reference would be assigned to >>>>> > another type. But in our HDL we need to know the types we are >>>>> > dealing with (we remove some of the dynamicism :) >>>>> > >>>>> > Yes, all "variable" intbv need "[:] = <new value>". >>>>> > >>>>> > I made changes to your original and it converts, but I did not >>>>> > check if it still passes the testbench: >>>>> > http://www.edaplayground.com/x/eW >>>>> > >>>>> > Note: conversion to Verilog will fail to compile with a Verilog >>>>> > compiler because some of the signal/variable names are reserved >>>>> > words (e.g. "real"). It has been on our todo list to check for >>>>> > reserved words in conversion. >>>>> > >>>>> > Regards, >>>>> > Chris >>>>> > >>>>> > >>>>> ------------------------------------------------------------------------------ >>>>> > Open source business process management suite built on Java and >>>>> Eclipse >>>>> > Turn processes into business applications with Bonita BPM >>>>> Community Edition >>>>> > Quickly connect people, data, and systems into organized >>>>> workflows >>>>> > Winner of BOSSIE, CODIE, OW2 and Gartner awards >>>>> > http://p.sf.net/sfu/Bonitasoft >>>>> > _______________________________________________ >>>>> > myhdl-list mailing list >>>>> > myh...@li... <mailto: >>>>> myh...@li...> >>>>> > https://lists.sourceforge.net/lists/listinfo/myhdl-list >>>>> > >>>>> > >>>>> > >>>>> > >>>>> > -- >>>>> > Atenciosamente/Regards >>>>> > André Castelan Prado >>>>> > >>>>> > >>>>> > >>>>> ------------------------------------------------------------------------------ >>>>> > Open source business process management suite built on Java and >>>>> Eclipse >>>>> > Turn processes into business applications with Bonita BPM Community >>>>> Edition >>>>> > Quickly connect people, data, and systems into organized workflows >>>>> > Winner of BOSSIE, CODIE, OW2 and Gartner awards >>>>> > http://p.sf.net/sfu/Bonitasoft >>>>> > >>>>> > >>>>> > >>>>> > _______________________________________________ >>>>> > myhdl-list mailing list >>>>> > myh...@li... >>>>> > https://lists.sourceforge.net/lists/listinfo/myhdl-list >>>>> > >>>>> >>>>> >>>>> -- >>>>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com >>>>> Python as a HDL: http://www.myhdl.org >>>>> VHDL development, the modern way: http://www.sigasi.com >>>>> World-class digital design: http://www.easics.com >>>>> >>>>> >>>>> ------------------------------------------------------------------------------ >>>>> Open source business process management suite built on Java and Eclipse >>>>> Turn processes into business applications with Bonita BPM Community >>>>> Edition >>>>> Quickly connect people, data, and systems into organized workflows >>>>> Winner of BOSSIE, CODIE, OW2 and Gartner awards >>>>> http://p.sf.net/sfu/Bonitasoft >>>>> _______________________________________________ >>>>> myhdl-list mailing list >>>>> myh...@li... >>>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list >>>>> >>>> >>>> >>>> >>>> -- >>>> Atenciosamente/Regards >>>> André Castelan Prado >>>> >>>> >>>> ------------------------------------------------------------------------------ >>>> Open source business process management suite built on Java and Eclipse >>>> Turn processes into business applications with Bonita BPM Community >>>> Edition >>>> Quickly connect people, data, and systems into organized workflows >>>> Winner of BOSSIE, CODIE, OW2 and Gartner awards >>>> http://p.sf.net/sfu/Bonitasoft >>>> _______________________________________________ >>>> myhdl-list mailing list >>>> myh...@li... >>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list >>>> >>>> >>> >>> >>> ------------------------------------------------------------------------------ >>> Open source business process management suite built on Java and Eclipse >>> Turn processes into business applications with Bonita BPM Community >>> Edition >>> Quickly connect people, data, and systems into organized workflows >>> Winner of BOSSIE, CODIE, OW2 and Gartner awards >>> http://p.sf.net/sfu/Bonitasoft >>> _______________________________________________ >>> myhdl-list mailing list >>> myh...@li... >>> https://lists.sourceforge.net/lists/listinfo/myhdl-list >>> >>> >> >> >> -- >> Atenciosamente/Regards >> André Castelan Prado >> > > > > -- > Atenciosamente/Regards > André Castelan Prado > -- Atenciosamente/Regards André Castelan Prado |
