Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module
Brought to you by:
jandecaluwe
From: Jan D. <ja...@ja...> - 2014-07-04 12:57:52
|
On 07/04/2014 02:38 PM, André Prado wrote: > I meant that you can't do this in VHDL but I thought that in MyHDL you could do that. http://myhdl.org/start/why.html#signals-and-variables-like-vhdl > > Thanks for the Explanation, I look forward to translate the code of my product from VHDL to MyHDL :), still in the learning process but the power of Python makes VHDL looks out dated hehe. > > Cheers > > > On Fri, Jul 4, 2014 at 9:33 AM, Christopher Felton <chr...@gm... <mailto:chr...@gm...>> wrote: > > On Fri, Jul 4, 2014 at 6:50 AM, André Prado <and...@gm... <mailto:and...@gm...>> wrote: > > So, I can't use the same signal as a signal and a variable. Just like VHDL :) > > > Not sure what you mean? You can mix the signal assignment > and variable assignment in VHDL? If you declare a signal you > need to use "<=" if a variable ":=". > > MyHDL only has one assignment operator, "=". But the types > need to match. You need to determine if you really want a signal > or a variable: > http://www.jandecaluwe.com/hdldesign/signal-assignments.html > > > What is the difference between assigning a value with [:] and without it? All the intbv values need a [:] ? > > > In Python everything is a reference > > x = intbv(0, min=-4, max=4) > y = intbv(0, min=-8, max=8) > # ... > x = 2 > y[:] = 4 > assert isinstance(x, intbv) # will fail > assert isinstance(y, intbv) # will pass > > The [:] indicates you are updating the value of the intbv type > (updating all the bits). If you didn't do this you would loose the > intbv information, because the reference would be assigned to > another type. But in our HDL we need to know the types we are > dealing with (we remove some of the dynamicism :) > > Yes, all "variable" intbv need "[:] = <new value>". > > I made changes to your original and it converts, but I did not > check if it still passes the testbench: > http://www.edaplayground.com/x/eW > > Note: conversion to Verilog will fail to compile with a Verilog > compiler because some of the signal/variable names are reserved > words (e.g. "real"). It has been on our todo list to check for > reserved words in conversion. > > Regards, > Chris > > ------------------------------------------------------------------------------ > Open source business process management suite built on Java and Eclipse > Turn processes into business applications with Bonita BPM Community Edition > Quickly connect people, data, and systems into organized workflows > Winner of BOSSIE, CODIE, OW2 and Gartner awards > http://p.sf.net/sfu/Bonitasoft > _______________________________________________ > myhdl-list mailing list > myh...@li... <mailto:myh...@li...> > https://lists.sourceforge.net/lists/listinfo/myhdl-list > > > > > -- > Atenciosamente/Regards > André Castelan Prado > > > ------------------------------------------------------------------------------ > Open source business process management suite built on Java and Eclipse > Turn processes into business applications with Bonita BPM Community Edition > Quickly connect people, data, and systems into organized workflows > Winner of BOSSIE, CODIE, OW2 and Gartner awards > http://p.sf.net/sfu/Bonitasoft > > > > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |