Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Christopher F. <chr...@gm...>]

On Fri, Jul 4, 2014 at 6:50 AM, André Prado <and...@gm...> wrote:

> So, I can't use the same signal as a signal and a variable. Just like VHDL
> :)
>

Not sure what you mean?  You can mix the signal assignment
and variable assignment in VHDL?  If you declare a signal you
need to use "<=" if a variable ":=".

MyHDL only has one assignment operator, "=".  But the types
need to match.  You need to determine if you really want a signal
or a variable:
http://www.jandecaluwe.com/hdldesign/signal-assignments.html


>
> What is the difference between assigning a value with [:] and without it?
> All the intbv values need a [:] ?
>

In Python everything is a reference

    x = intbv(0, min=-4, max=4)
    y = intbv(0, min=-8, max=8)
    # ...
    x = 2
    y[:] = 4
    assert isinstance(x, intbv)   # will fail
    assert isinstance(y, intbv)   # will pass

The [:] indicates you are updating the value of the intbv type
(updating all the bits).  If you didn't do this you would loose the
intbv information, because the reference would be assigned to
another type.  But in our HDL we need to know the types we are
dealing with (we remove some of the dynamicism :)

Yes, all "variable" intbv need "[:] = <new value>".

I made changes to your original and it converts, but I did not
check if it still passes the testbench:
http://www.edaplayground.com/x/eW

Note: conversion to Verilog will fail to compile with a Verilog
compiler because some of the signal/variable names are reserved
words (e.g. "real").  It has been on our todo list to check for
reserved words in conversion.

Regards,
Chris