Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

So, I can't use the same signal as a signal and a variable. Just like VHDL
:)

What is the difference between assigning a value with [:] and without it?
All the intbv values need a [:] ?

Thank you Christopher, Will get back to if you if I get more errors hehe






On Fri, Jul 4, 2014 at 8:28 AM, Christopher Felton <chr...@gm...>
wrote:

> <snip>
>>
>>
>> KeyError: 'real_reg' and a long traceback list error
>>
>> The module is not 100% functional yet, It's the first time I am doing and
>> I confess I am struggling with this different paradigm, It's not VHDL and
>> it's not Matlab, it's somewhere in the middle hah.
>>
>>
> One issue, "real_reg" is being used as a variable (real_reg[:]) and as
> a signal (real_reg.next).  If you resolve this inconsistency it might
> fix the error.
>
> The testbench must not exercise those branches, otherwise you
> should of had an attribute error.
>
> Regards,
> Chris
>
>
>
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-- 
Atenciosamente/Regards
André Castelan Prado