Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Christopher F. <chr...@gm...>]

>
> <snip>
>
> KeyError: 'real_reg' and a long traceback list error
>
> The module is not 100% functional yet, It's the first time I am doing and
> I confess I am struggling with this different paradigm, It's not VHDL and
> it's not Matlab, it's somewhere in the middle hah.
>
>
One issue, "real_reg" is being used as a variable (real_reg[:]) and as
a signal (real_reg.next).  If you resolve this inconsistency it might
fix the error.

The testbench must not exercise those branches, otherwise you
should of had an attribute error.

Regards,
Chris